The present application relates generally to power density management in a circuit board. More specifically, the present application is directed to distribution of power vias in a multi-layer circuit board.
Printed circuit boards (“PCB”) are generally fabricated from a plurality of laminated layers. Each of the layers typically includes a core fabricated from an insulating material, such as FR-4, epoxy glass, polyester or synthetic resin bonded paper, for example. Typically, a copper layer is bonded to one or both sides of the core. Circuits or “traces” are formed on the copper by applying a mask and removing unneeded copper. The individual layers are then laminated together to form the PCB.
A power distribution network for a PCB is typically designed to transfer power among different layers of the PCB. For instance, power transfer between layers can occur when a voltage regulator (i.e., a source) and the power sinks (e.g., chips or connectors) are placed on different sides of the PCB or when metal shapes are added on internal layers to attenuate high current density in certain regions, such as in proximity of voltage regulator outputs. Thick power “vias” are commonly used to transfer energy between the layers. Each of the power vias is typically expected to carry a portion of the total current transferred between layers. However, some power vias transfer much more current than others.
There is a physical limit to the current that a single via can carry before incurring in a thermal problem. In an extreme case, a via could melt, creating unwanted shorts and failures due to excess current. High current density in solid planes and dielectric in close proximity of the vias carrying more current can generate high temperatures, which is not desirable, particularly if thermally-sensitive components are in the area. Localized increases in temperature can increase metal resistivity, resulting in higher voltage drops during operation as compared to design expectations.